Method for producing thin substrate layers

ABSTRACT

The present invention relates to a method of producing very thin substrate layers, particularly thin semiconductor areas, which may comprise integrated circuits. In the method two substrates ( 1, 2 ) are bonded by their faces via one or several intermediate connecting layers ( 3, 4 ). At least one of the bonding layers or the face of one of the substrates is structured before in such a way that channel-shaped recesses ( 5 ) are formed which permit a lateral penetration of an etching agent. The resulting wafer stack is thinned from one side down to the desired thickness of the layer. Finally, this thin layer is detached from the remaining substrate by introduction of the etching agent into the channel-shaped recesses. This detaching process is a low-price wet chemical process that does not expose the chip and the added value integrated thereon to any risk.

FIELD OF APPLICATION

The present invention relates to a method of producing thin substratelayers, specifically thin semiconductor zones possibly containingintegrated circuits.

It may be expedient for many present and future applications ofelectronic components and integrated circuits (ICs) in particular torestrict the overall thickness of these ICs or the semiconductor zoneswith the ICs to a few micrometers. Such thin circuits present a very lowmass and have a very small overall height. They are mechanicallyflexible, adapt themselves to the thermo-mechanical behaviour of asubstrate and reduce problems in disposal on account of their smallvolume. All these advantages may gain even more importance within thegeneral framework of future disposable electronics. As early as to datethin electronic devices and circuits for fields of application such asflat panel displays, where ICs are bonded to glass, mechatronics, wherethe ICs are bonded to metal, and high-power electronics (transistors,thyristors, diodes with vertical conduction) are of great interest.

In silicon technology, integrated circuits are manufactured onsubstrates, the so-called wafers. These wafers consist ofmono-crystalline silicon which present, in typical cases, a thickness of700 μm and a diameter of 200 mm at present and of 300 mm in the nearfuture. The definition of the thickness of the substrates to 700 μmoffers several aspects in terms of manufacturing technology and alsophysics. For instance, the precision and the yield in slicing or sawingof the crystal rods drawn from the melt and their subsequent polishing,on the one hand, are important, on the other hand the mechanicalstability and a sufficient thermal mass must be ensured during theactual processing of the ICs.

After the production of the integrated circuits or devices in terms ofsemiconductor technology the wafers and hence the individual chips ofthe wafer must be thinned to a residual thickness as small as 200 μm andeven down to 120 μm at present in order to be suitable for integrationinto housings or on pc boards in particular.

Processing of the devices or circuits on cantilever wafers which arealready thinned is normally ruled out because the mechanical stability,the thermal load-bearing capacity et. is by no means sufficient to thisend below a thickness of 50 μm. Moreover, the process development andthe entire manufacturing equipment are designed and set for wafers ofconventional thickness.

The thinning of the completely processed wafer Is normally realised bypolishing. In this process the rear side of the wafer is mechanicallyremoved by means of a polishing paste and suitable abrasive-carryingagents up to the desired residual thickness. Being a monocrystallinesubstance, silicon cannot be subjected to chipping operations. In thecourse of polishing rather so-called micro-fissures occur, which are dueto the crystalline nature and which may propagate up to the deviceregion of the wafer and destroy the functional operability of thecircuits if the process is inappropriately managed. As a consequence ofthis situation the residual thickness of the silicon substrates, thatcan be achieved by polishing, is restricted, as a rule to a thicknesscorresponding to 5 to 10 times the size of the abrasive grains.

One possibility to solve this problem consists in the use of very fineabrasive grains up to diameters of a few hundreds of nanometers, Thisentails, however, a dramatic reduction of the removal rate so that thethinning process requires a very long time.

For a reduction of the residual thickness below the values occurring inthe conventional grinding process it is necessary, as a rule, to employparticularly gentle polishing methods. An appropriate process whichattempts to combine the advantages of grinding, wet-chemical etching andso-called CMP (chemical mechanical polishing) is published, forinstance, in the paper by D. Bollmann et al., Abstract No. 2115,Proceedings, The Electrochemical Society Meeting, Paris 1997. As analternative, wet and also dry etching methods have been tried. Thelatter processes, however, lead to a high thermal load on the substrateand the devices applied thereon, with the necessary amount of theremoval rate.

On principle, these methods involve the thinning of the wafer afterprocessing of the circuits. The processes leading to thinning are thusperformed on a wafer on the surface of which the entire high added valuein chip production is already accumulated. Faulty thinningcorrespondingly leads to a reduction of the yield and hence in highlosses in value. Moreover, the observation of the desired residualthickness is rendered rather difficult on account of the reducedpossibility of (local) measurement of the residual thickness, which isimpaired by the implemented devices.

A fundamental way out of the problems Involved in thinning of waferspresenting a high accumulated added value and in the complex thicknessmeasurement consists in the application of so-called SOI wafers. SOIwafers carry an insulating layer buried just below the surface, as arule in the form of an SiO₂ layer. There are several methods availablefor the production of such SOI wafers (cf., for instance, W. P. Maszaraet al.: “SOI Materials for Mainstream CMOS Technology”, in: SOITechnology and Devices VII, ed.: S. Christoloveanu, The ElectrochemicalSociety Proceedings 97-23, 1997) which will be outlined in thefollowing.

In SOS (silicon on sapphire) techniques an epitactical silicon layer isdeposited on a polished Al₂O₃ crystal. This approach is successful as aresult of the approximately equal lattice constant of both materials.However, crystalline Al₂O₃ wafers must be used, which renders thismethod very expensive and is applicable only in the case of extremelyhigh-price applications.

In ZMR (zone melting recrystallization) technique poly-silicon isdeposited on a wafer covered with SiO₂ and then crystallised by a localfusing and solidifying process. The crystal quality, the crystallitesize, etc. of these wafers does, as a matter of fact, no longer satisfythe demands current in today's CMOS technology.

In the SIMOX (Separation of implanted oxygen) technique a high-dose ionimplantation just below the surface of the silicon wafer creates astoichiometric SiO2 layer which, in the case of an appropriate processmanagement, i.e. thorough healing of the crystal damage caused byimplantation, leaves the extremely thin silicon layer monocrystallinethat is located thereabove and will carry devices later on.

In the BESOI (bonded etched-back silicon on insulator) technique twooxidized silicon wafers are fixedly fastened on each other by thermalbonding and covalent bonds so established. Then one of the two wafers isthinned back to the useful thickness. A specific variant of the BESOItechnology (“SmartCut® OR IonCut) uses special methods of thinning whichare based on the implementation of a layer created by means of ionimplantation and buried below the surface, along which layer the usefullayer is split off that is bonded onto the second wafer (manipulating)wafer. This may be achieved by forming gas bubbles by means of hydrogenor helium implantation (cf. European Patent EP-A 0 533 551 or M. Bruelet al. in_“Unibond SOI Wafers Achieved by Smart-Cut® Process” in: SoITechnology and Devices VIII, ed.: S. Christoloveanu, TheElectromechanical Society Proceedings 97-23, 1997) or by detaching afusing intermediate layer (cf. German Patent DE 1{circumflex over ( )}9546 179 A1). In both cases the production of a BESOI wafer is successfulwithout repeated grinding or etching of major parts of a monocrystallinewafer laboriously produced before.

SOI wafers produced according to the SIMOX and BESOI processes have beendeveloped up to a stage ready for application in the past few years.They are applied in the fields of application high-temperatureelectronics and “low power electronics” to an ever-increasing extent andare commercially available in high numbers of units.

Such SOI wafers may be used for the production of extremely thin ICs.The subsequent removal of the thick carrier wafer by grinding, wet ordry chemical etching, etc. may then be stopped expediently at the buriedlayer. In the case of mechanical grinding, and specifically its refinedform of chemical mechanical polishing (CMP) the buried SiO₂ layer mayserve as the mechanically hard stop layer. Furthermore, it is possiblethat mechanical defects such as micro-cracks cannot or only hardlypenetrate through the amorphous SiO₂ layer. In the case of wet chemicaldown-etching the high selectivity (better than 1:100) of the normallyoxidizing silicon etching process results in a reliable etching stop atthe buried oxide layer. In the case of the less selective dry etchingprocesses, e.g. by application of NF₃ plasma, the SiO₂ layer may equallyserve as selective stop layer. In view of the decreasing lateralconductivity, furthermore a local self-restriction of the etchingprocess may be utilised.

One advantage in the application of SOI wafers resides in the aspectthat the process resulting in subsequent thinning, i.e. theimplementation of a buried layer underneath the silicon of the usefulwafer, is performed before the processing proper in terms ofsemiconductor technology. As a consequence, firstly a high added valueis not endangered, and secondly it is possible to use particularlysimple optical or even acoustic measures of measuring the thicknessbecause at this stage the wafer does not yet present any localstructures, metals, etc. which render a non-contacting and precisemeasurement of the thickness more difficult or preclude it entirely.

However, the removal of the thick manipulating wafer by means ofgrinding or etching means that the monocrystalline silicon is destroyedover a substantial thickness, with a resulting expenditure in terms oftime.

The present invention is therefore based on the problem of proposing alow-cost and rapid method of producing thin substrate layers, which issuitable to produce extremely thin ICs and avoids the afore-describedproblems.

This problem is solved with the method according to claim 1. Expedientembodiments of the method are the subject matters of the dependentclaims. Moreover, the claims 29 to 47 define substrate systems whichconstitute an essential key product in realising the method.

In the inventive method, which will also be referred to as RevSOI(reversible SOI technique) a first substrate and a second substrate arebonded to each other by their faces via one or several intermediatebonding layers. At least one of the bonding layers or the face of one ofthe substrates is so configured that it presents channelshaped recessespermitting a lateral penetration of an etching agent. Subsequently, thefirst substrate is thinned from the rear side down to a thin substratelayer. This thin substrate layer is subsequently detached from thesecond substrate by the introduction of the etching agent into thechannel-shaped recesses.

The two substrates are preferably semiconductor wafers for theproduction of ICs.

These wafers are processed in the same manner as that common within thegeneral framework of IC or single-device production. Sagging does notoccur on the wafers as long as the width of the channels (preferably0.1-2 μm) ranges at a fraction of the thickness of the useful layer ofthe semiconductor layer (typically 0.5-20 μm).

After processing the structured bonding layer serves as sacrificiallayer. This layer is laterally accessible, at any time, either from theside of the wafer or, in the case of a preferred embodiment, as soon asthe hermetically sealed wafer edge is removed/opened. This isautomatically done particularly when the wafer is subdivided to formchips. Before, the thin chips are expediently fixed on a carriersubstrate.

The separation of the useful layer from the bulk layer is preferablycarried out by wet chemical etching. In this step the etching agent(such as HF) is aspirated into the channels under the effect ofcapillary forces. The driving forces are the chemical reaction and thesurface tension. The rate of flow or the throughput quantity,respectively, is described in approximation by the Hagen-Poiseuille lawand depends on the channel lumen in the fourth power. In large-areachips or generally in the separation of large-area wafer zones theremoval of the reaction products (e.g. SiF₄) may be assisted byultrasound, centrifugal force, thermal gradients (generated, forinstance, by means of IR laser radiation) etc.

Moreover, vertical holes or slots may be provided or etched in theuseful layer for the supply and extraction of the etching agent. Forsupplying or extracting the etching agent, the cleaving or sawing frameproduced between the chips is expediently used.

The channel-shaped recesses need not necessarily extend along linearorientations. They need not present a rectangular cross-section eithernecessarily. In particular, the vertical walls or edges of the channelsmay also present an orientation varying from 90° relative to thesurface. Due to the specific engineering features of the etchingoperation, particularly in the case of etching under the mask in wetchemical etching, this edge bevelling may occur all by itself. On theother hand, however, special methods may be applied for edge bevellingor edge projection. Edge projection or cantilevering leads to theadvantage of a relative enlargement of the bonding oxide area. Methodsof taking an influence on the inclination of the etching edge are commonto those skilled in the art within the general framework of the wet anddry etching techniques applied in semiconductor technology.

The aforementioned method may be extended or modified by the provisionthat the channels are not or not exclusively created in the bondinglayer or layers but rather completely or partly in the substrates assuch. In the case of a rectangular cross-section, this may lead to anenlargement of the lumen. A practical limit is set by the mechanicalcharacteristics of the substrates (buckling under thermal strain,warping).

In particular, one can dispense with an oxide cover in at least one ofthe two wafers to be bonded. In this case the natural oxide, which isalways present on wafers exposed to air, serves as bonding area.

In a preferred embodiment the fact is utilised that the buriedinsulating layer is freely accessible in BESOI wafers before both wafersare joined to form the BESOI assembly. It is also accessible forstructuring of the bonding oxide in particular. One or both of the twowafers typically carries an SiO₂ layer roughly 1 μm thick. Prior tojoining trenches are etched in one or both oxides, to which end thewafer edge carries a coherent annular oxide zone. Then both wafers arejoined by thermal bonding in the usual manner, and one of the two wafersis thinned by means of one of the current thinning methods (grinding,etching, lonCut) described with respect to the BESOI technique toachieve the desired thickness of the useful layer.

Subsequently, circuits are formed with the usual technology on thisBESOI wafer. During production, for which thermal and also vacuum or gasphase processes in particular are employed, the wafer is hermeticallyclosed on the edge by the oxide ring. After completion of the circuitsand opening of the coherent edge layer located on the wafer or alsoafter subdivision of the wafer into chips the buried oxide layer,specifically the channels in the oxide provided therein, is laterallyaccessible. An etching agent such as hydrofluoric acid may penetrateinto these channels and etch into the bonding oxide. The thin chip,which is preferably previously fixed by its face on a holding substratefor mechanical support, is typically detached within the range ofminutes in the case of edge lengths of roughly 10 mm.

The detachment is a low-price wet chemical process which hardly exposesthe chip and the added value integrated thereon to any risk.

It is particularly simple to check the thickness of the layer inthinning of the BESOI wafer by the presence of the burled cavities(trenches) with local resolution by means of acoustical microscopy.

As an alternative, the lonCut technique is applicable where grinding andmeasurement of the thickness of the layer are avoided.

The trenches present in the bonding layer produce an expedient effect onthe bonding operation. It is common knowledge that wafers with ascratched surface have better bonding properties. This is traced back tothe easier diffusion of residual gases, adsorbed moisture, etc. duringthe beginning bonding operation for which the presence of water(hydrophilic surface) is expedient.

The wafer edge or possibly also various elementary zones are preferablyfree of laterally accessible channels. This can be clearly seen both inFIG. 2b and in FIG. 3. The wafer should be hermetically sealed afterbonding and tolerate all processes applied within the general frameworkof semiconductor device production.

The BESOI bonding process may be performed in particular in a vacuum orequally in special oxidizing or reducing atmospheres.

One advantage of accessibility of the sacrificial layer or “zipperlayer”during the production of the RevSoi wafer resides in the fact thatthe cavities may be filled with specific gases.

In an expedient embodiment the bonding operation is performed with theaddition of trace gases, helium in particular. On account of theenclosed gas it is particularly simple to check the bonded wafer fortightness (helium leakage test).

In another embodiment doping gases are enclosed in order to create ahighly doped buried layer or a gettering layer.

The essential feature of the lateral accessibility of the insulatingoxide layer may also be utilised in an approach to metallize theinternal surfaces of the channels by means of a liquid or a gaseousmetal compound and organometallic compounds in particular.

The present invention will be described again in the following byembodiments with reference to the Figures wherein:

FIG. 1 is a schematic illustration of a flowchart of the inventiveproduction process;

FIG. 2 shows examples of structuring the bonding layers on the substratesurface; and

FIG. 3 illustrates a further example of structuring as well as examplesof the cross-sectional shape of the channel-shaped recesses on thebonding areas of the substrates.

FIG. 1 shows a schematic example of a flowchart of the entire productionprocess.

Initially two wafers (1, 2), whereof each carries an oxide layer (3, 4)on a surface, are made available. The oxide layer (4) of one of thewafers is so structured that strip-shaped channels (5) are created whichextend over the entire surface. The structures are transferred by one ortwo preferably non-adjusted photo techniques into the oxide (4). The twowafers are bonded by their oxidized surfaces, preferably by the SFB(silicon fusion bonding) technique, as is illustrated in FIGS. 1a and 1b.

Then a process follows like in case of BESOI production, wherein thestack of wafers created by bonding is thinned from the rear side of oneof the substrates down to the desired thickness of the semiconductorzone (1 a).

Then the normal IC process, e.g. a CMOS process, may be performed toproduce circuits and/or single devices (6) in the semiconductor layer (1a) of the thinned substrate (1).

After this step dry etching or wet etching of trenches (7) takes place,as is illustrated in FIG. 1e), for the subsequent subdivision of thechips, which trenches are, however, substantially narrower than usual,mechanically created cleaving or sawing lines. The trenches (7) extendup to the buried structured oxide layer (4). Mechanical cleaving orsawing of the trenches is possible, too.

In the etching process the surface of the ICs (6) must be protected.This is done by applying a layer (8), e.g. a nitride of photo resistlayer. This protective layer (8) may then either be tom off again orremain as protective layer for the chip detaching process. When thelayer (8) is removed before a new protective layer (10), preferably aphoto resist layer, musts be applied before the detaching process, as isillustrated in FIG. 1f.

By the preceding trench etching process the channels (5) were exposed inthe buried oxide layer (4) (cf. FIG. 1e) so that in the subsequentdetaching process, which is preferably performed with HF, the etchingliquid can penetrate into the channels (5) and detach the individualchips (9) from below, as is evident from FIG. 1f. In this detachingprocess the selectivity of oxide relative to silicon is utilized inetching.

The wafer can be mechanically supported from the face by means of amanipulating wafer prior to detachment. This manipulating wafer should,however, present appropriate channels for introducing the etchingliquid.

The subdivided, completely processed chips (9) may be applied on asubstrate (11) subsequently.

A particularly expedient configuration is illustrated in FIG. 2a thatshows the employed wafer both in a plan view and a cross-sectional view.Both wafers (1, 2) carry an SiO₂ layer (3, 4), roughly 1 μm thick, thatis structured with typical line widths (s, b) of 1-2 μm approximately.Moreover, the right side of the Figure shows also the starting wafer (1)prior to structuring as an example. The layer is structured by a wetchemical and non-adjusted process, i.e. this structuring process ishence suitable for low-cost production. Restrictions in terms ofstructure and orientation of these SiO₂ trenches or channels may derivefrom the anisotropic mechanical properties of the crystalline wafers(wafer sagging).

In this example, the layers are structured on both Si wafers (1, 2) insuch a way that the trenches extend at an angle of 90° relative to eachother after the wafers have been joined. With this provision a betterdistribution of the etching liquid can be achieved in the subsequentdetaching process. In this example, two different trench structures areselected for illustration purposes. The SiO₂ layer of the first wafer(1) presents, for instance, trenches which penetrate through the entirethickness h1 of the layer whilst the trenches present a depth as smallas H3 in the other wafer (2) so that a residual thickness H2 (h3+h2=h1)of the layer is retained over the entire area.

FIG. 2b finally illustrates a modification of the structure of the twolayers of the wafer. Here each of the layers remained in the edge zoneof the wafers remained unstructured so that after wafer joining ahermetically sealed wafer stack is obtained.

These wafers shown in FIG. 2 are joined to each other and thinned fromone side, as is explained with reference to FIG. 1. The resulting waferwith the thin semiconductor zone (1 a) as useful layer and integrated“zipper layer” constitutes the basis of the inventive RevSOI (reversibleSOI) technique.

In all embodiments the geometric configuration of the channels (5),specifically the shape of their lateral extension, the subdivision intoareas separated from each other in a hermetically sealed manner isentirely free of the formation of bonding islets etc. However, it shouldduly consider the marginal conditions “bonding force” and wafer orsubstrate bending, which are necessary for stable bonding, and ensure atthe same time an efficient transfer of the etching agent.

Exemplary shapes of the channels (5) in both substrates are rectangularstructures, round, meandering or polygon-type structures. The structureshould, on the one hand, offer a maximum mechanical stability for thesilicon membrane (1 a) and, on the other hand, render the detachingprocess as simple and rapid as possible. This means that afterpenetration into the channels (5) the etching liquid should corrode asuniformly as possible on all points and ensure a rapid detachment of theICs. The spacings of the channels are variable, too. Examples ofdifferent cross-sectional shapes of the channels (5) are illustrated inFIG. 3, where the structuring may be performed also as far as into thesubstrate as such.

The bonding layer may be structured in the form of islets or in strip orpuncti-form shape FIG. 3 illustrates an islet-type structuring in theform of a lattice structure (right side: non-structured layer, leftside: structured layer).

The islet-shaped structuring presents the advantage, in addition to thebetter distribution of the etching liquid, that mechanical strain willbe avoided in the wafer. Continuous strips as channels produce a greaterinfluence than a bonding layer structured in the form of islets.

The cross-section through the channels may equally be optimized inconsideration of the aforementioned aspects, i.e. mechanical stabilityand rapid detachment of the ICs.

Either the surfaces of both wafers or substrates to be bonded, or onlyone of them, may be structured. For better bonding of the two wafersboth should present an oxide layer. However, this Is not necessarilynecessary.

Doped oxides, particularly the PSG, TEOS, PECVD, LPCVD, APCVD and BPSGoxides used in CMOS processes, may also be used instead of pure oxide asmaterials for the bonding layers. This provision is suitable to increasethe etching rate in chip detachment.

As a variant of the method for separation or detachment it is alsopossible to apply the anodic oxidation, specifically for silicon wafers.In this variant an electrical voltage is applied to both silicon wafersor wafer layers, respectively, which are bonded via the insulatinglayer, which voltage results in a flow of current and in an electrolyticdecomposition of the electrodes by means of anodic oxidation. In thisprocess the liquid migrates under the bonding oxide, with a resultingdetachment and separation of both elementary silicon wafers due toenlargement of the volume in oxide formation.

The bonding strength of wafers structured in accordance with the presentinvention is reduced by the reduced bonding area. Whilst the normalbonding force of conventional BESOI wafers ranges at <800 kp/cm² itamounts still to 200 kp/cm² in the lattice structure illustrated in FIG.3, due to the bonding area factor reduced to 25%. This is sufficient inany case to resist the thermal strain occurring during the furtherprocessing (thermal budget in chip production) and also theexpansion-induced pressure of the gas enclosed in bonding (max. 4 bar at1200 K). A channel web width (pitch) of 1 μm in typical cases does notresult in any troublesome local or global bending with a useful siliconthickness of 10 μm in typical cases.

What is claimed is:
 1. Method of producing thin substrate layerscomprising: a first semiconductor substrate and a second substrate arebonded by their faces via one or several intermediate bonding layers,with at least one of said bonding layers or the face of one of saidsubstrates presenting channel-shaped recesses having a cross-sectionsuch that a lateral penetration of an etching agent will becomepossible; said first substrate is thinned from the rear side down to asubstrate layer; and said substrate layer is detached from said secondsubstrate by introducing the etching agent into said channel-shapedrecesses.
 2. Method according to claim 1, wherein that saidchannel-shaped recesses are created in the form of a strip pattern. 3.Method according to claim 1, wherein that said channel-shaped recessesare created in the form of a lattice structure.
 4. Method according toclaim 1, wherein that said channel-shaped recesses are created in saidbonding layer in such a way that they do not completely penetratethrough said bonding layer.
 5. Method according to claim 1, wherein thatsaid channel-shaped recesses are created with a cross-sectional area inthe range from 0.1 to 10 μm².
 6. Method according to claim 1, whereinthat said first substrate is thinned down to a substrate layer with athickness of less that 50 μm.
 7. Method according to claim 1, whereinthat said channel-shaped recessed are so created that they do not extendup to the edge of said substrates so that the interstice formed betweenboth substrates by said channel-shaped recesses is hermetically sealedby bonding said substrates.
 8. Method according to claim 1, wherein thatsaid channel-shaped recesses are so created that several closed interiorzones are formed between both substrates, which are hermetically sealed.9. Method according to claim 1, wherein that a quartz substrate is usedas said second substrate.
 10. Method according to claim 1, wherein thatthe two elementary substrates of a BESOI wafer are used as first andsecond substrates, with said bonding layers being the insulator layersof the BESOI wafer.
 11. Method according to claim 1, wherein that priorto detachment said substrate layers is subjected to processing forproducing devices and/or integrated circuits in said substrate layer.12. Method according to claim 11, wherein that prior to detachment, thebonded substrates are subdivided into smaller units, particularly chips,with single circuits.
 13. Method according to claim 11, wherein thatprior to detachment, said bonded substrates are subdivided into smalllinear units having a line width of one chip or a multiple thereof, andline lengths corresponding to the length of several chip up to thecomplete substrate width.
 14. Method according to claim 11, wherein thatprior to detachment, vertical openings or trenches, specifically in theform of cleaving or sawing lines, are created between individualintegrated circuits via which the etching agent is introduced. 15.Method according to claim 1, wherein that said bonding layer is an oxidelayer or SiC layer.
 16. Method according to claim 15, wherein that aninsulating layer consisting of SiO₂ in pure or doped form, particularlyBSG or BPSG, is used as oxide layer.
 17. Method according to claim 1,wherein that hydrofluoric acid or an etching solution substantiallycontaining hydrofluoric is used as etching agent.
 18. Method accordingto claim 1, wherein that a gas or plasma appropriate for etching is usedas etching agent, which burns in the cavities between both substrates inresponse to the application of an electric field.
 19. Method accordingto claim 1, wherein that the bonding of said two substrates is performedby a bonding operation in the presence of a gas so that this gas isenclosed in said channel-shaped recesses.
 20. Method according to claim19, wherein that an inert, an oxidizing or a reducing gas is used. 21.Method according to claim 19, wherein that a gas suitable for testingthe bond for leakage, specifically helium, is used either alone or inadmixed form.
 22. Method according to claim 19, wherein that a gasserving for silicon doping, such as PH₃, POCl or B₂H₆, is enclosed insaid channel-shaped recesses when the substrates are bonded.
 23. Methodaccording to claim 1, wherein that said etching agent is passed throughsaid channel-shaped recesses by means of pressure.
 24. Method accordingto claim 1, wherein that the detachment is assisted by an electriccurrent that results in chemical reactions on both substrates heldtogether by said bonding layer.
 25. Method according to claim 1, whereinthat the detachment is supported and thus accelerated by ultrasound,heat and/or centrifugal force.
 26. Method according to claim 1, whereinthat said channel-shaped recesses are coated with a thin metal layercompletely or partly on laterally oriented areas under the action of ametal-containing compound.
 27. Method according the claim 26, whereinthat the coating is performed by means of thermally decomposingorganometallic compound or a currentless or galvanic deposition.